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? semiconductor components industries, llc, 2001 april, 2001 rev. 6 1 publication order number: cs8129/d cs8129 5.0 v, 750 ma low dropout linear regulator with lower reset threshold the cs8129 is a precision 5.0 v linear regulator capable of sourcing 750 ma. the reset threshold voltage has been lowered to 4.2 v so that the regulator can be used with 4.0 v microprocessors. the lower reset threshold also permits operation under low battery conditions (5.5 v plus a diode). the reset 's delay time is externally programmed using a discrete rc network. during power up, or when the output goes out of regulation, reset remains in the low state for the duration of the delay. this function is independent of the input voltage and will function correctly as long as the output voltage remains at or above 1.0 v. hysteresis is included in the delay and the reset comparators to improve noise immunity. a latching discharge circuit is used to discharge the delay capacitor when it is triggered by a brief fault condition. the regulator is protected against a variety of fault conditions: i.e. reverse battery, overvoltage, short circuit and thermal runaway conditions. the regulator is protected against voltage transients ranging from 50 v to +40 v. short circuit current is limited to 1.2 a (typ). the cs8129 is packaged in a 5 lead to220 and a 16 lead surface mount package. features ? 5.0 v 3.0% regulated output ? low dropout voltage (0.6 v @ 0.5 a) ? 750 ma output current capability ? reduced reset threshold for use with 4.0 v microprocessors ? externally programmed reset delay ? fault protection reverse battery 60 v, 50 v peak transient voltage short circuit thermal shutdown http://onsemi.com to220 five lead t suffix case 314d 1 5 to220 five lead tva suffix case 314k to220 five lead tha suffix case 314a 1 5 1 see general marking information in the device marking section on page 8 of this data sheet. device marking information so16l dw suffix case 751g 1 16 device package shipping ordering information cs8129yt5 to220* straight 50 units/rail cs8129ytha5 to220* vertical 50 units/rail cs8129ytva5 to220* horizontal 50 units/rail *five lead. cs8129ydw16 so16l so16l 46 units/rail 1000 tape & reel cs8129ydwr16
cs8129 http://onsemi.com 2 pin connections so16l pin 1. v in 2. reset 3. gnd 4. delay 5. v out 1 to220 5 lead nc delay 1 16 nc nc gnd reset gnd gnd gnd gnd v out(sense) nc nc nc v out v in + + gnd reset v out latching discharge v discharge figure 1. block diagram v in over voltage shutdown thermal shutdown delay comparator + bandgap reference antisaturation and current limit regulated supply for circuit bias preregulator + charge current generator q s r v out (sense) error amplifier delay absolute maximum ratings* rating value unit input operating range 0.5 to 26 v power dissipation internally limited peak transient voltage (46 v load dump @ 14 v v in ) 50, 60 v output current internally limited electrostatic discharge (human body model) 4.0 kv junction temperature 55 to +150 c storage temperature range 55 to +150 c lead temperature soldering: wave solder (through hole styles only) (note 1.) reflow (smd styles only) (note 2.) 260 peak 230 peak c 1. 10 second maximum. 2. 60 seconds max above 183 c. *the maximum package power dissipation must be observed.
cs8129 http://onsemi.com 3 electrical characteristics (40 c t a 125 c, 40 t j 150 c, 6.0 v in 26 v, 5.0 ma i out 500 ma, r reset = 4.7 k w to v out unless otherwise noted.) note 3. characteristic test conditions min typ max unit output stage (v out) output voltage 4.85 5.0 5.15 v dropout voltage i out = 500 ma 0.35 0.60 v supply current i out = 10 ma i out = 100 ma i out = 500 ma 2.0 6.0 55 7.0 12 100 ma ma ma line regulation 6.0 v v in 26 v, i out = 50 ma 5.0 50 mv load regulation 50 ma i out 500 ma, v in = 14 v 10 50 mv ripple rejection f = 120 hz, v in = 7.0 to 17 v, i out = 250 ma 54 75 db current limit 0.75 1.20 a overvoltage shutdown 32 40 v reverse polarity input voltage dc v out 0.6 v, 10 w load 15 30 v thermal shutdown guaranteed by design 150 180 210 c reset and delay functions delay charge current v delay = 2.0 v 5.0 10 15 m a reset threshold v out increasing, v rt(on) v out decreasing, v rt(off) 4.05 4.00 4.35 4.20 4.50 4.45 v v reset hysteresis v rh = v rt(on) v rt(off) 50 150 250 mv delay threshold charge, v dc(hi) discharge, v dc(lo) 3.25 2.85 3.50 3.10 3.75 3.35 v v delay hysteresis 200 400 800 mv reset output voltage low 1.0 v < v out < v rt(l) , 3.0 k w to v out 0.1 0.4 v reset output leakage v out > v rt(h) current 0 10 m a delay capacitor discharge voltage discharge latched aono, v out > v rt 0.2 0.5 v delay time c delay = 0.1 m f, note 4. 16 32 48 ms 3. to observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable. 4. assuming ideal capacitor. delaytime c delay v delay threshold charge i charge c delay 3.5 10 5 (typ)
cs8129 http://onsemi.com 4 package lead description package lead # so16l to220 5 lead lead symbol function 1 1 v in unregulated supply voltage to ic. 16 5 v out regulated 5.0 v output. 4, 5, 11, 12, 13 3 gnd ground connection. 8 4 delay timing capacitor for reset function. 6 2 reset cmos/ttl compatible output lead. reset goes low whenever v out drops be- low 6.0% of it's regulated value. 14 n/a v out(sense) remote sensing of output voltage. typical performance characteristics v in (v) 01234 6 8 10 5 figure 2. quiescent current vs. input voltage over temperature 30 25 20 15 10 5 0 i cq (ma) 9 figure 3. quiescent current vs. input voltage over load resistance v in ( v ) 012 34 5 120 100 0 i cq . (ma) 80 60 40 20 room temp r load = 6.67 w 35 r load = 10 w r load = 25 w r load = no load 40 45 50 55 67 8910 figure 4. output voltage vs. input voltage over temperature figure 5. v out vs. v in over r load 7 v in (v) 01234 6 8 10 5 3.0 2.5 2.0 1.5 1.0 0.5 0 v out (v) 9 r load = 25 w 25 c 3.5 40 c 125 c 4.0 4.5 5.0 5.5 7 r load = 25 w 25 c 40 c 125 c v in (v) 0123 4 6 8 10 5 3.0 2.5 2.0 1.5 1.0 0.5 0 v out (v) 9 room temp 3.5 r load = 6.67 w 4.0 4.5 5.0 5.5 7 r load = 10 w r load = no load
cs8129 http://onsemi.com 5 typical performance characteristics output current (ma) 0 800 100 200 700 300 400 80 40 20 20 60 0 100 line reg. (mv) 600 500 output current (ma) load regulation (mv) figure 6. line regulation vs. output current output current (ma) 0 100 200 500 600 800 60 40 30 20 10 0 quiescent current (ma) 50 output current (ma) 0 100 200 300 400 500 600 400 300 200 100 0 dropout voltage (mv) 500 700 600 700 figure 7. load regulation vs. output current frequency (hz) 10 0 10 1 10 2 10 3 10 4 10 5 70 50 40 30 20 0 rejection (db) 60 10 6 10 7 10 8 10 i out = 250 ma 80 90 figure 8. dropout voltage vs. output current figure 9. quiescent current vs. output current figure 10. ripple rejection figure 11. output capacitor esr 80 60 40 100 v in = 626 v temp = 25 c temp = 125 c temp = 40 c v in = 14 v temp = 25 c temp = 125 c temp = 40 c 080 0 100 200 700 300 400 80 40 20 20 60 0 100 600 500 80 60 40 100 800 900 800 40 c 125 c 25 c 70 80 90 100 300 400 700 v in = 14 v 40 c 125 c 25 c c out = 10 m f, esr = 1.0 & 0.1 m f, esr = 0 c out = 10 m f, esr = 1.0 w c out = 10 m f, esr = 1.0 w output current (ma) 10 0 10 1 10 2 10 3 10 3 10 1 10 0 10 1 10 2 10 4 esr (ohms) 10 2 10 3 c o = 47/68 m f stable region c o = 68 m f c o = 47 m f
cs8129 http://onsemi.com 6 figure 12. reset circuit waveform v rh (1) (2) (2) (3) v rl v dh v dc(hi) v dc(lo) delay t delay v dis reset v rt(off) v rt(on) v out (1) = no delay capacitor (2) = with delay capacitor (3) = max: reset voltage (1.0 v) circuit description the cs8129 reset function has hysteresis on both the reset and delay comparators, a latching delay capacitor discharge circuit, and operates down to 1.0 v. the reset circuit output is an open collector type with on and off parameters as specified. the reset output npn transistor is controlled by the two circuits described (see block diagram on page 2). low voltage inhibit circuit this circuit monitors output voltage, and when output voltage is below the specified minimum causes the reset output transistor to be in the on (saturation) state. when the output voltage is above the specified level, this circuit permits the reset output transistor to go into the off state if allowed by the reset delay circuit. reset delay circuit this circuit provides a programmable (by external capacitor) delay on the reset output lead. the delay lead provides source current to the external delay capacitor only when the alow voltage inhibito circuit indicates that output voltage is above v rt(on) . otherwise, the delay lead sinks current to ground (used to discharge the delay capacitor). the discharge current is latched on when the output voltage is below v rt(off) . the delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. this feature ensures that a controlled reset pulse is generated following detection of an error condition. the circuit allows the reset output transistor to go to the off (open) state only when the voltage on the delay lead is higher than v dc(hi) . figure 13. test & application circuit c in * 100 nf delay v out r rst c out ** 10 m f to 100 m f reset cs8129 *c in is required if regulator is far from the power source filter . **c out is required for stability. v in gnd 4.7 k w delay 0.1 m f the delay time for the reset function is calculated from the formula: delay time c delay v delay threshold i charge delay time c delay( f) 3.2 10 5 if c delay = 0.1 m f, delay time (ms) = 32 ms 50%: i.e. 16 ms to 48 ms. the tolerance of the capacitor must be taken into account to calculate the total variation in the delay time.
cs8129 http://onsemi.com 7 application notes stability considerations the output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (25 c to 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provides this information. the value for the output capacitor c out shown in figure 13 should work for most applications, however it is not necessarily the optimized solution. to determine an acceptable value for c out for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next lar ger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: raise the temperature to the highest specified operating temperature. v ary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 14) is: p d(max) v in(max) v out(min) i out(max) v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r q ja can be calculated: r ja 150 c t a p d (2) the value of r q ja can then be compared with those in the package section of the data sheet. those packages with r q ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. figure 14. single output regulator with key performance parameters labeled smart regulator ? control features i out i in i q v in v out
cs8129 http://onsemi.com 8 heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r q ja . r ja r jc r cs r sa (3) where: r q jc = the junctiontocase thermal resistance, r q cs = the casetoheatsink thermal resistance, and r q sa = the heatsinktoambient thermal resistance. r q jc appears in the package section of the data sheet. like r q ja , it too is a function of package type. r q cs and r q sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers. marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week to220 five lead cs8129 awlyww 1 1 cs8129 awlyyww 16 so16l
cs8129 http://onsemi.com 9 package dimensions to220 five lead t suffix case 314d04 issue e q 12345 u k d g a b 5 pl j h l e c m q m 0.356 (0.014) t seating plane t dim min max min max millimeters inches a 0.572 0.613 14.529 15.570 b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 g 0.067 bsc 1.702 bsc h 0.087 0.112 2.210 2.845 j 0.015 0.025 0.381 0.635 k 0.990 1.045 25.146 26.543 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 u 0.105 0.117 2.667 2.972 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. to220 five lead tva suffix case 314k01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. dim min max min max millimeters inches a 0.560 0.590 14.22 14.99 b 0.385 0.415 9.78 10.54 c 0.160 0.190 4.06 4.83 d 0.027 0.037 0.69 0.94 e 0.045 0.055 1.14 1.40 f 0.530 0.545 13.46 13.84 g 0.067 bsc 1.70 bsc j 0.014 0.022 0.36 0.56 k 0.785 0.800 19.94 20.32 l 0.321 0.337 8.15 8.56 m 0.063 0.078 1.60 1.98 q 0.146 0.156 3.71 3.96 s 0.146 0.196 3.71 4.98 u 0.460 0.475 11.68 12.07 w 55 r 0.271 0.321 6.88 8.15 a u d g b t m 0.356 (0.014) m q 5 pl q k f j c e t s l 12345 seating plane r m w
cs8129 http://onsemi.com 10 to220 five lead tha suffix case 314a03 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 0.043 (1.092) maximum. dim a min max min max millimeters 0.572 0.613 14.529 15.570 inches b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 f 0.570 0.585 14.478 14.859 g 0.067 bsc 1.702 bsc j 0.015 0.025 0.381 0.635 k 0.730 0.745 18.542 18.923 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 s 0.210 0.260 5.334 6.604 u 0.468 0.505 11.888 12.827 t seating plane l s e c f k j optional chamfer 5x d 5x m p m 0.014 (0.356) t g a u b q p so16l dw suffix case 751g03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 package thermal data parameter to220 five lead so16l unit r q jc typical 2.1 23 c/w r q ja typical 50 105 c/w
cs8129 http://onsemi.com 11 notes
cs8129 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs8129/d smart regulator is a registered trademark of semiconductor components industries, llc (scillc). north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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